周山
Post By：2010-3-8 10:51:00 [只看該作者]
接通電源后，一直停留在windows CE正在啟動(dòng)狀態(tài)，如何解決？
主題：EM9260無(wú)法正常啟動(dòng) 共有36085人關(guān)注過(guò)本帖 |
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周山 |
1樓 |
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EM9260無(wú)法正常啟動(dòng) Post By：2010-3-8 10:51:00 [只看該作者]
接通電源后，一直停留在windows CE正在啟動(dòng)狀態(tài)，如何解決？
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zxw |
2樓 |
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Post By：2010-3-8 12:09:00 [只看該作者]
能不能選接上超級(jí)終端，把啟動(dòng)信息發(fā)到我們公司的郵箱里
具體是什么原因，需要看一看啟動(dòng)信息 |
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周山 |
3樓 |
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Post By：2010-3-9 16:16:00 [只看該作者]
啟動(dòng)信息已經(jīng)發(fā)到你們的support郵箱，麻煩看看，如何處理
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周山 |
4樓 |
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Post By：2010-3-9 16:32:00 [只看該作者]
LLD_Rea?RomBOOT
> INFO : Low Level Init : OK Starting eboot ... Master Clock is 48054841 Hz Master Clock is 50070885 Hz Master Clock is 50070885 Hz 晧諠丼erial Initialized Microsoft Windows CE Ethernet Bootloader Common Library Version 1.1 Built Dec 18 2008 17:35:16 Master Clock is 50070885 Hz Microsoft Windows CE Ethernet Bootloader 1.7 for the AT91SAM9260EK board (built Dec 19 2008) Adaptation performed by ADENEO (c) 2005 ->LLD_InitNandChipset K9F5608U0D Master Clock is 50070885 Hz --------------------------------------- --- Configuring Chip Select 3 --- --------------------------------------- --- Desired timings --- --------------------------------------- dwNWE_SETUP 0 dwNCS_WR_SETUP 0 dwNRD_SETUP 0 dwNCS_RD_SETUP 0 dwNWE_PULSE 40 dwNCS_WR_PULSE 60 dwNRD_PULSE 40 dwNCS_RD_PULSE 80 dwNRD_CYCLE 100 dwNWE_CYCLE 60 dwClockPeriod_ns 19 --------------------------------------- --- Real timings --- --------------------------------------- dwNWE_SETUP 0 dwNCS_WR_SETUP 0 dwNRD_SETUP 0 dwNCS_RD_SETUP 0 dwNWE_PULSE 57 dwNCS_WR_PULSE 76 dwNRD_PULSE 57 dwNCS_RD_PULSE 95 dwNRD_CYCLE 133 dwNWE_CYCLE 95 Master Clock is 50070885 Hz --------------------------------------- --- Configuring Chip Select 3 --- --------------------------------------- --- Desired timings --- --------------------------------------- dwNWE_SETUP 19 dwNCS_WR_SETUP 0 dwNRD_SETUP 19 dwNCS_RD_SETUP 0 dwNWE_PULSE 38 dwNCS_WR_PULSE 76 dwNRD_PULSE 38 dwNCS_RD_PULSE 76 dwNRD_CYCLE 76 dwNWE_CYCLE 76 dwClockPeriod_ns 19 --------------------------------------- --- Real timings --- --------------------------------------- dwNWE_SETUP 19 dwNCS_WR_SETUP 0 dwNRD_SETUP 19 dwNCS_RD_SETUP 0 dwNWE_PULSE 38 dwNCS_WR_PULSE 76 dwNRD_PULSE 38 dwNCS_RD_PULSE 76 dwNRD_CYCLE 76 dwNWE_CYCLE 76 Nand Flash correctly Initialized WDTC_WDMR = 3FFF2FFF WDTC_WDMR = 8000 Press [ENTER] to launch image stored in flash or [SPACE] to cancel. Initiating image launch in 5 seconds. 4 seconds. 3 seconds. 2 seconds. 1 seconds. 0 seconds. System ready! Preparing for download... memset 80067000 len=1a240c0 FMD_DirectRead - OEMReadImgFromFlash - Addr = 60000 Download successful! Jumping to image at 0x80068000 (physical 0x20068000)... Master Clock is 50070885 Hz ]ス懡萃丆E Kernel for ARM (Thumb Enabled) Built on Feb 8 2007 at 23:36:51 ProcessorType=0926 Revision=5 sp_abt=ffff5000 sp_irq=ffff2800 sp_undef=ffffc800 OEMAddressTable = 80068020 Windows CE Firmware Init +OALIntrInit +OALIntrMapInit -OALIntrMapInit +SOCPioIntrInit() -SOCPioIntrInit() +OALIntrStaticTranslate(17, 21) -OALIntrStaticTranslate -OALIntrInit(rc = 1) Initialize driver globals Zeros area... pDrvGlobalArea 0x80058000 size 0x800 (0x80058800 -0x80058000) Initialize driver globals Zeros area...done Master Clock is 50070885 Hz Master Clock is 50070885 Hz --------------------------------------- --- Configuring Chip Select 1 --- --------------------------------------- --- Desired timings --- --------------------------------------- dwNWE_SETUP 0 dwNCS_WR_SETUP 0 dwNRD_SETUP 0 dwNCS_RD_SETUP 0 dwNWE_PULSE 0 dwNCS_WR_PULSE 0 dwNRD_PULSE 0 dwNCS_RD_PULSE 0 dwNRD_CYCLE 0 dwNWE_CYCLE 0 dwClockPeriod_ns 19 --------------------------------------- --- Real timings --- --------------------------------------- dwNWE_SETUP 0 dwNCS_WR_SETUP 0 dwNRD_SETUP 0 dwNCS_RD_SETUP 0 dwNWE_PULSE 0 dwNCS_WR_PULSE 0 dwNRD_PULSE 0 dwNCS_RD_PULSE 0 dwNRD_CYCLE 0 dwNWE_CYCLE 0 OALTimerInit +OALTimerInit Master Clock is 50070885 Hz Test : 0xc39 g_oalTimer.msecPerSysTick : 0x1 g_oalTimer.countsPerMSec : 0xc39 g_oalTimer.countsMargin : 0x0 g_oalTimer.maxPeriodMSec : 0x14e g_oalTimer.countsPerSysTick : 0xc39 g_oalTimer.actualMSecPerSysTick : 0x1 g_oalTimer.actualCountsPerSysTick : 0xc39 g_oalTimer.curCounts : 0x0 Master Clock is 50070885 Hz -OALTimerInit pDrvGlobalArea->bEboot == TRUE. Forcing Clean Object store +OEMPowerManagerInit -OEMPowerManagerInit avant OALKitlStart - force clean (@0x81adedb4 = 0x1) = TRUE OALKitlStart Firmware Init Done. +OEMInitWatchDogTimer AT91SAM926x_DispWatchDog 8000! force clean (@0x81adedb4 = 0x1) = TRUE EM9X60 Init Master Clock is 50070885 Hz --------------------------------------- --- Configuring Chip Select 5 --- --------------------------------------- --- Desired timings --- --------------------------------------- dwNWE_SETUP 33 dwNCS_WR_SETUP 11 dwNRD_SETUP 33 dwNCS_RD_SETUP 11 dwNWE_PULSE 429 dwNCS_WR_PULSE 473 dwNRD_PULSE 429 dwNCS_RD_PULSE 473 dwNRD_CYCLE 517 dwNWE_CYCLE 517 dwClockPeriod_ns 19 --------------------------------------- --- Real timings --- --------------------------------------- dwNWE_SETUP 38 dwNCS_WR_SETUP 19 dwNRD_SETUP 38 dwNCS_RD_SETUP 19 dwNWE_PULSE 437 dwNCS_WR_PULSE 475 dwNRD_PULSE 437 dwNCS_RD_PULSE 475 dwNRD_CYCLE 532 dwNWE_CYCLE 532 EM9260 Init LCD240128_WriteByte LCD Type = 6, Started Sp=ffffc7cc OEMIoControl: Unsupported Code 0x10100b4 - device 0x0101 func 45 RTC status 92 +OALIoCtlHalInitRTC(...) OEMIoControl: Unsupported Code 0x101008c - device 0x0101 func 35 ->LLD_InitNandChipset K9F5608U0D +OALIntrRequestSysIntr(1, 0x8d, 0x00000000) -OALIntrRequestSysIntr(sysIntr = 16) Master Clock is 50070885 Hz --------------------------------------- --- Configuring Chip Select 3 --- --------------------------------------- --- Desired timings --- --------------------------------------- dwNWE_SETUP 19 dwNCS_WR_SETUP 0 dwNRD_SETUP 19 dwNCS_RD_SETUP 0 dwNWE_PULSE 38 dwNCS_WR_PULSE 76 dwNRD_PULSE 38 dwNCS_RD_PULSE 76 dwNRD_CYCLE 76 dwNWE_CYCLE 76 dwClockPeriod_ns 19 --------------------------------------- --- Real timings --- --------------------------------------- dwNWE_SETUP 19 dwNCS_WR_SETUP 0 dwNRD_SETUP 19 dwNCS_RD_SETUP 0 dwNWE_PULSE 38 dwNCS_WR_PULSE 76 dwNRD_PULSE 38 dwNCS_RD_PULSE 76 dwNRD_CYCLE 76 dwNWE_CYCLE 76 +OALIntrReleaseSysIntr(16) -OALIntrReln S m FMD_GetBlockStatus::Logical block 0x135 is marked as bad FMD_GetBlockStatus::Logical block 0x137 is marked as bad FMD_GetBlockStatus::LogFMD_GecFMD_GetBlockStatus::FMD_GetBlcFMD_GetBlockStatus::Logical block 0x450 is marked as bad FMD_GetBlockStatus::Logical block 0x459 is marked as bad FMD_GetBlockStatus::Logical block 0x4E0 is marked as bad FMD_GetBlockStatus::Logical block 0x6FF is marked as bad OEMIoControl: Unsupported Code 0x10100c4 - device 0x0101 func 49 |
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Post By：2010-3-9 17:00:00 [只看該作者]
看來(lái)是內(nèi)核出了問(wèn)題。建議把板子寄回我們來(lái)做進(jìn)一步檢查，一般收到的當(dāng)天就會(huì)處理好，并通過(guò)快件給你發(fā)回去。
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